1. Field of the Invention
The present invention relates to a technology for maintaining coherency between cache memories.
2. Description of the Related Art
A central processing unit (CPU) uses a cache memory as a solution to data delay problems, which occurs among main memories. The cache memory has a hierarchical structure with respect to the main memories, and ones having a plurality of hierarchies have been currently used.
The cache memory is referred to as a first level cache and a second level cache in order of being closer to a CPU. Generally, the cache memory is configured such that as the cache memory is closer to the CPU, it has a smaller capacity, although access becomes faster, and as the cache memory is closer to the main memory, it has a larger capacity, although access becomes slower.
In the conventional cache memory, a copy of a tag with respect to the first level cache is stored in the second level cache, and the second level cache uses the copy of the first-level cache tag to obtain tag information of the first level cache, thereby eliminating mutual inconsistency between the first level cache and the second level cache (maintain the coherency).
FIG. 19 is a diagram showing stages until a state of a first level cache is obtained according to a conventional technology. As shown in FIG. 19, in the conventional technology, the mutual inconsistency between the first level cache and the second level cache is eliminated in such a manner that when a second-level cache tag is accessed by a physical index, the copy of the first-level cache tag is accessed by using a virtual index included in the second level cache (that is, two-step access) to ascertain a registration state of the first level cache.
Japanese Patent Application Laid-open No. H10-301850 discloses a technology to improve decoding efficiency in a cache-line state by associating a state bit field with each cache line included in the cache. Japanese Patent Application Laid-open No. H8-235061 discloses a technology enabling to track inclusion of a data cache by involving a directory having an inclusion bit, a command bit, and a data bit in a common second level cache.
Japanese Patent Application No. 2004-222401 discloses a technology in which the copy of the first-level cache tag can be searched, using a search result of the tag to the second level cache, by integrating the copy of the first-level cache tag with the second level cache, thereby enabling to eliminate a delay due to two-step access.
In this conventional technology, however, while the two-step access can be eliminated to enable speed-up of the machine cycle of the cache memory, there is a problem in that use efficiency relating to the copy of the first-level cache tag integrated with the second level cache is low, because of the hierarchical structure of the cache memory, and limited resources of the second level cache cannot be efficiently used.
This is attributable to a large capacity of the second level cache as compared with the capacity of the first level cache, that is, to a difference in the number of entries between the first and second level caches. If it is tried to include the first-level cache tag in the tag to the second level cache, fundamentally, there is a portion that is never used by the capacity difference therebetween. For example, if it is assumed that the second level cache has 96 k entries, whereas the first level cache has 2 k entries, the copy portion of the first-level cache tag used in the second level cache has a use efficiency of 2% at maximum.
Further, due to the improvement of recent semiconductor technologies, the latest CPUs include multicores. The second level cache accessed from the multicores has a smaller difference in the number of entries than that at the time of including a single core. However, because an amount of information required for the copy of the first level cache increases, as a result, the use efficiency of the integrated tag decreases, and this problem becomes more serious.
Further, to improve the use efficiency, the above conventional technologies can be used. In the conventional technologies, however, two-step access needs to be performed to ascertain the registration state of the first level cache. Therefore, a delay problem due to the two-step access occurs, and it is difficult to speed up the machine cycle.
That is, it is an important to improve the machine cycle by eliminating the delay due to the two-step access, and to efficiently use the limited resources of the cache memory.